QSGMII (Quad Serial Gigabit Media Independent Interface) is a MAC-to-PHY interface that combines four SGMII ports into a single 5 Gb/s serial link, so one SerDes lane in each direction carries four 10/100/1000 Mbit/s Ethernet ports. It is used between a multi-port switch or processor and multi-port gigabit PHYs, where four separate SGMII links would need four times the lanes and pins. An 8-port gigabit PHY connects to the switch through two QSGMII links. USXGMII is a different interface family that carries one or more ports at speeds from 10 Mbit/s to 10 Gbit/s over a single SerDes. VOOHU is an authorized distributor of JLSemi Ethernet PHYs, including the 8-portJL2308andJL2388with QSGMII.
QSGMII saves SerDes lanes and pins on multi-port boards. SGMII carries one port at 1.25 Gbit/s over one differential pair in each direction, so eight copper ports would need eight SGMII links: 16 pairs and 32 data pins, not counting clocks. QSGMII carries four ports on one 5 Gb/s lane, so the same eight ports need two links: four pairs and eight data pins. Fewer high-speed traces between the switch and the PHY also make the board easier to route. Each port inside the link still runs at 10, 100 or 1000 Mbit/s, so QSGMII is aimed at gigabit copper ports.
For single-port boards, the parallel interfaces MII, RMII and RGMII and single-port SGMII are compared inMII vs RMII vs RGMII vs SGMII.
An 8-port gigabit PHY connects to the switch through two QSGMII links, four ports per link; each copper port still has its own magnetics and RJ45. Port grouping is illustrative; the PHY datasheet defines the actual mapping.
| Interface | Ports per link | Port speeds | Serial rate | Defined by |
|---|---|---|---|---|
| SGMII | 1 | 10/100/1000 Mbit/s | 1.25 Gbit/s | Cisco |
| QSGMII | 4 | 10/100/1000 Mbit/s each | 5 Gb/s | Cisco QSGMII specification |
| USGMII (JLSemi lists an octal form, O-USGMII) | 4 or 8 | Gigabit ports | 5G or 10G SerDes | Cisco USGMII specification |
| USXGMII | 1, or several in the multi-port form | 10M, 100M, 1G, 2.5G, 5G, 10G | 5G or 10G SerDes | Cisco USXGMII specification |
Sources: AMD'sQSGMII product guide (PG029)and Cisco'sUSGMII and USXGMII specifications. Both ends of a link must run the same mode: a QSGMII PHY needs a MAC or switch port that supports QSGMII, and an SGMII-only port cannot talk to it directly.
USXGMII is a Cisco-defined interface that carries Ethernet at any rate from 10 Mbit/s to 10 Gbit/s over a single SerDes, in single-port and multi-port (USXGMII-M) versions, at a 5G or 10G SerDes rate. It exists because SGMII and QSGMII stop at 1 Gbit/s per port, while 2.5G, 5G and 10G copper ports need a faster link. QSGMII fits four gigabit ports per lane; USXGMII fits ports that run faster than 1 Gbit/s, or a MAC that must cover every rate from 10M to 10G on one interface. For a single 2.5G port, PHYs also use other SerDes modes: theJL42012.5G PHY, for example, connects over SGMII, H-SGMII or 2500BASE-X.
| Part | Ports | Port speeds | Host interface | Package |
|---|---|---|---|---|
| JL2308-PI | 8 | 10/100/1000 Mbit/s | 2 × QSGMII or 1 × O-USGMII | LQFP-128 E-PAD |
| JL2388-PI | 8 | 10/100/1000 Mbit/s | 2 × QSGMII or 1 × O-USGMII | LQFP-128 E-PAD |
| JL4201-NI | 1 | 10/100/1000 Mbit/s and 2.5 Gbit/s | SGMII, H-SGMII, 2500BASE-X | 48-pin QFN |
Ports, interfaces and packages are taken from each part's JLSemi product brief. The JL2308 and JL2388 each give a direct connection to a MAC or switch port over two QSGMII links or one O-USGMII link; compare their briefs for LED, clock and test features. Commercial and industrial temperature grades are listed on the product pages, for exampleJL2308-PCand JL2308-PI. Browse theJL2308andJL2388series, or compare all JL-series PHYs in theEthernet PHY selector.
产品JL2308-PI
产品JL2388-PI
方案/solution-ethernet/
Q1: What is the QSGMII speed?
A QSGMII link runs at 5 Gb/s and carries four Ethernet ports, each at 10, 100 or 1000 Mbit/s. That is four times the 1.25 Gbit/s of SGMII, which is how four gigabit ports share one lane in each direction.
Q2: Can QSGMII connect to SGMII?
Not directly. QSGMII carries four ports on one 5 Gb/s lane, while an SGMII port expects one port at 1.25 Gbit/s. Use a MAC or switch port that supports QSGMII, a PHY that offers SGMII, or a device that converts between the two. Some switch and SoC SerDes lanes can be configured for either mode, so check the datasheet.
Q3: What is the difference between USXGMII and SGMII?
SGMII carries one port at up to 1 Gbit/s over a 1.25 Gbit/s link. USXGMII carries one port, or several in its multi-port form, at any rate from 10 Mbit/s to 10 Gbit/s over a 5G or 10G SerDes, so it suits 2.5G, 5G and 10G copper PHYs.
Send your switch chip or processor, the SerDes modes its ports support, and the number and speed of your copper ports through oursample and support request form. Our FAE team can check whether a QSGMII PHY such as the JL2308 matches your MAC, suggest the LAN transformers or MagJacks for each port and help review the interface configuration. Samples are available for evaluation, and selected parts are free of charge. Our FAE team will be glad to confirm the options for your project.
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