MII vs RMII vs RGMII vs SGMII: Which MAC-to-PHY Interface Should You Use?

MII, RMII, RGMII and SGMII are the interfaces that connect the Ethernet MAC in a processor, FPGA or switch to the PHY chip that drives the cable. MII and RMII carry 10/100 Mbit/s: MII uses 4-bit transmit and receive paths clocked at 25 MHz, and RMII halves that to 2 bits on a shared 50 MHz reference clock to save pins. RGMII and SGMII carry up to 1000 Mbit/s: RGMII is a 12-pin parallel bus that uses both edges of a 125 MHz clock, while SGMII is a 1.25 Gbps serial link with one differential pair in each direction. Choose the interface your MAC provides at the speed you need, then pick a PHY with the same interface. VOOHU supplies JL-series Ethernet PHYs with MII, RMII, RGMII, SGMII and QSGMII interfaces.

#What is the difference between MII, RMII, RGMII and SGMII?

*Pin counts depend on which optional signals are included: TI's SSZT718 gives 15 for MII and 9 for RMII, while TI's DP83TC811S-Q1 datasheet gives 14 and 7. RGMII is 12 and SGMII 4 or 6 in both. The MDC/MDIO management interface, which all of them use alongside, is extra. The full gigabit version, GMII, needs 24 pins, which is why RGMII and SGMII replaced it on most boards.

#MII vs RMII: which one for 100 Mbit/s Ethernet?

Both carry the same 10/100 Mbit/s traffic; the difference is pins and clocking. MII has separate transmit and receive clocks supplied by the PHY and 4-bit data paths. RMII moves two bits per cycle of a single 50 MHz reference clock that both the MAC and the PHY use, which brings the count down to 7 to 9 pins, depending on how they are counted. That 50 MHz clock comes from the MAC, the PHY or a separate 50 MHz oscillator, so decide which source drives it and keep that trace short.

RMII is the usual choice for microcontrollers, where pins are scarce. Use MII when your MAC offers only MII, or when an FPGA design already has the pins. The JL1101BR-NI is an RMII PHY for 100BASE-TX, 10BASE-T and 100BASE-FX in a 24-pin, 4 mm × 4 mm QFN. The JL1111B-NI is listed with MII, and its JL11x1 brief also lists RMII mode. Filter by RMII PHYs in the selector.

#RGMII vs SGMII: which is better for Gigabit Ethernet?

It depends on what your MAC offers and how the board is laid out.

• RGMII is a parallel, single-ended bus: 4 data lines, a control line and a clock in each direction. It needs no SerDes, so it is common on processors and microcontrollers with a gigabit MAC. The cost is 12 traces that must be length-matched and kept short, and a clock-to-data delay to manage.
• SGMII is a serial, differential link at 1.25 Gbps over two pairs, or three if the PHY also sends a clock. It needs a SerDes on the MAC side, as found on FPGAs, switch chips and network processors. It uses far fewer pins, and its low-voltage differential signaling reduces EMI compared with RGMII.

If your MAC has both, RGMII is simpler for a short connection on the same board, and SGMII suits designs that need fewer, differential traces, for example to a PHY on another board. The JL2101C-NI is an RGMII Gigabit PHY whose RGMII I/O can run at 3.3, 2.5 or 1.8 V; the JL2201 series is listed with RGMII, and the JL2xx1 brief also lists SGMII for it. The JL4201-NI connects over SGMII, H-SGMII or 2500BASE-X and supports 10/100/1000 Mbit/s and 2.5 Gbit/s. Compare RGMII PHYs and SGMII PHYs in the selector.

What is RGMII delay, and why does it matter?

At 1000 Mbit/s, RGMII launches data and clock edges together, so the receiver needs the clock delayed relative to the data to sample correctly. That delay can come from the PCB or from the devices. Texas Instruments, for example, specifies in its DP83867 datasheet that without internal delay the clock trace must add more than 1.5 ns of extra delay. Many MACs and PHYs can add the delay internally instead, a mode often written RGMII-ID. Decide which side adds the delay for transmit and for receive, and make sure it is added exactly once: no delay, or a delay added twice, can stop a gigabit link while 100 Mbit/s still works, because a 25 MHz clock leaves far more timing margin than 125 MHz.

#What are the key differences between SGMII and QSGMII?

SGMII carries one port. QSGMII combines four SGMII ports into a single 5 Gb/s interface, so a switch chip can reach four copper ports through one SerDes lane in each direction instead of four. It is the usual interface between a multi-port switch and its PHYs. The JL2308-PI is an 8-port 10/100/1000 Mbit/s PHY that connects to the switch over two QSGMII links, or one O-USGMII link, in a 128-pin LQFP; the JL2388 series offers the same interfaces.

#Which PHY interface should you choose?

VOOHU is an authorized distributor of these JLSemi PHYs. Interfaces, speeds and packages above are taken from each series' JLSemi product brief. Browse all of them in the Ethernet PHY selector. On the cable side, every copper PHY needs a matching LAN transformer or RJ45 jack with integrated magnetics; see PHY wiring principles, and for what a PHY does overall, what an Ethernet PHY chip is.

#FAQ

QIs RGMII DDR?

Yes, at 1000 Mbit/s. RGMII sends 8 bits per 125 MHz clock cycle over 4 data lines by using both clock edges: the lower 4 bits on the rising edge and the upper 4 bits on the falling edge. At 10 and 100 Mbit/s, double data rate is not needed and the clock runs at 2.5 or 25 MHz.

QIs RGMII compatible with RMII?

No. RMII uses 2-bit data paths on a shared 50 MHz reference clock, while RGMII uses 4-bit paths with separate transmit and receive clocks, so the pins and timing do not match. A MAC and a PHY must use the same interface. Some PHYs offer several, selected by strap pins or registers.

QWhat speed is SGMII?

The SGMII line runs at 1.25 Gbps in each direction and carries Ethernet at 10, 100 or 1000 Mbit/s. At lower speeds, the data is repeated to fill the line: at 100 Mbit/s, each byte is sent 10 times. SGMII auto-negotiation tells the MAC which speed the PHY has linked at.

QWhat is the difference between SGMII and 1000BASE-X?

1000BASE-X is the IEEE 802.3 gigabit fiber protocol. It runs at 1000 Mbit/s only, and its speed is not negotiated, so both ends must be set to the same speed. SGMII also carries 10 and 100 Mbit/s and uses its auto-negotiation to pass the PHY's link speed to the MAC, which is why copper PHYs use it.

Get help matching a PHY to your MAC

Send your processor, FPGA or switch chip, its MAC interface, the port speed and the number of ports through our sample and support form. Our FAE team can suggest a JL-series PHY with a matching interface and the LAN transformer or MagJack to go with it, and help check the interface mode and clocking against your MAC. Samples are available for evaluation, and selected parts are free of charge. Our FAE team will be glad to confirm the options for your project.

VOOHU supplies RJ45 and SFP connectors, LAN and PoE transformers, common mode chokes and Ethernet PHY and switch chips from Suzhou, China, to more than 1,500 customers.