How to choose USB 2.0 common mode inductor? Impedance, differential insertion loss and ESD layout verification - VOOHU

How to choose a USB 2.0 common mode inductor is often proposed after the prototype has been able to enumerate and the transmission is basically normal: the radiation exceeds the standard after connecting a long line, the line is occasionally disconnected during plugging and unplugging, or the main control is reset during electrostatic testing. The most common mistake at this time is to change materials just by looking at a "75Ω, 90Ω or 120Ω" number. What the common mode inductor needs to suppress is the common mode noise flowing in the same direction on the two lines. At the same time, it must try to retain the D+ and D− differential signals. Therefore, the selection must also check the common mode impedance, differential insertion loss, symmetry, DC boundary and board-level layout.

1. How to choose USB 2.0 common mode inductor: first confirm that the fault is really common mode noise

The purpose of the USB common mode inductor is to suppress codirectional noise, not to fix all differential link problems.

The ideal differential current has opposite directions in the two windings, and the magnetic fluxes roughly cancel out; the common-mode current has the same direction, and the device presents a higher impedance to it. This is the core of the role of USB common mode inductors. However, discontinuous backflow in the connector, asymmetry of the D+ and D− branches, cross-slit reference planes, long test points, or impedance mismatch at the PHY end may all convert differential energy into common mode energy first. If you only rely on increasing the common-mode impedance to cover up these structural problems, the prototype may become quieter on a certain cable, but sacrifice the eye diagram or exceed the standard again after changing the cable.

First use spectrum, cable current and A/B board to determine the noise path

It is recommended to keep a baseline board without a common-mode inductor or with a 0Ω jumper available, and record the radiation spectrum, cable common-mode current, bit errors or transmission stability under the same host, equipment, cables, service loads and placement methods. If the anomaly changes significantly with D+/D− symmetry, shielding grounding, or cable layout, the layout and return flow should be repaired first; if the common-mode current peak is clear, the peak value drops after adding candidate devices, and the link margin is still sufficient, then proceed to device comparison.Murata USB 2.0 signal line noise caseIt shows how to install a common mode choke and check the eye diagram simultaneously under specific CISPR 25 test conditions, but its noise reduction figures cannot be extrapolated to guaranteed values for other boards.

2. What is the impedance of the USB common mode inductor: first separate the three "impedance" concepts

The 75Ω, 90Ω, and 120Ω on the product page are typical values of common mode impedance, not USB differential impedance.

The impedance of the USB common mode inductor cannot be discussed apart from the test frequency. The typical common-mode impedance value given on the product page is used to describe the device's ability to suppress common-mode current, while the 90Ω of the USB high-speed differential channel is the transmission line target, and the physical meanings of the two are different.TI USB Layout GuideIt is pointed out that USB 2.0 high-speed connection uses a differential characteristic impedance of 90Ω±15%, and emphasizes that D+ and D− should be short, matched and maintain a continuous reference plane. Interpreting a nominal 90Ω common-mode inductor as "exactly matching USB 90Ω" will confuse the device common-mode parameters with the PCB differential transmission line parameters.

Differential insertion loss, echo and mode conversion determine how much headroom is left in the link

Higher common mode impedance is not automatically better. Winding-to-winding coupling, parasitic capacitance, package pads, and two-wire imbalance all affect differential insertion loss, return loss, and differential-to-common-mode mode conversion.TDK Signal Line Common Mode Filter Selection GuideListing USB 2.0 as a 480Mbps application and giving specific device directions according to the interface rate shows that interface matching cannot rely solely on a low-frequency or single-point impedance field. The VOOHU public page currently does not fully expand the differential S parameters, test frequency points and USB eye diagrams required for this article. Therefore, the three material numbers are only candidates for A/B/C samples, and no direct adaptation commitment is made.

RDC, rated current, and rated voltage are boundary conditions and cannot replace signal verification.

The public page can also check the DC resistance, rated current, rated voltage and insulation resistance. These fields are used to confirm winding voltage drop, temperature rise, bias and insulation boundaries and do not indicate that differential signals have passed. USB D+/D− typically does not use rated current to determine bandwidth; similarly, lower RDC does not offset inappropriate parasitics. During procurement screening, "open DC fields" and "high-frequency fields to be confirmed in specifications" should be managed in separate columns to avoid mistaking easily comparable numbers for the final criteria.

3. Where to place the USB common mode inductor: The order of connector, ESD and PHY must be determined together.

The recommended order is connector-ESD-common mode inductor-PHY/MCU, but the chip data shall prevail.

Where to place the USB common mode inductor should be answered from the energy entrance and protected area boundaries.TI USB Layout GuideIt is recommended that USB 2.0 dedicated ESD devices be placed as close to the connector as possible; if there is a real need for a common mode inductor, it should also be placed close to the connector and the ESD device should be located further outside. Therefore, the common USB 2.0 common mode inductor ESD sequence is "connector-ESD-common mode inductor-PHY/MCU". In this way, the electrostatic current is first discharged near the entrance, and the common mode inductor then suppresses the common mode noise propagated into the cable or board. Different chips, ground partitions and interface structures still need to comply with the current layout recommendations of PHY and ESD manufacturers.

D+ and D− must be of equal length and environment, and no long branches should be left at the front or rear of the device.

Common mode inductors are physically small, but false fanout can create larger discontinuities. The two lines from the connector to ESD, common mode inductor and then to the controller should maintain similar line width, spacing, number of vias and reference planes; avoid sharply opening the differential pair on one side of the device, avoid long T-shaped test points, and do not cross the ground plane gap. There must be a clear boundary between the unprotected area and the sensitive area within the board, and the ESD leakage circuit cannot bypass the digital ground and return for a long distance. If it is necessary to change layers, the reflow vias should be placed in pairs and close together and confirmed by impedance calculation and actual measurement.

Reserved schematic diagram does not mean that any device can be temporarily inserted

It is recommended that the first version of the PCB reserves a controlled bypass solution for the common mode inductor position, such as DNP or short-circuit configuration in the same package, to facilitate same-board A/B testing; however, the bypass pad itself will also change the channel. The device orientation, pin correspondence and recommended pads must come from the current specifications. Just because they are all 2012 sizes does not mean that the default pads and winding pins are exactly the same. The mass production BOM needs to retain the complete material number suffix, and the alternative material list must also lock the S parameters, packaging, pads and mating verification results.

4. Establish an A/B/C verification matrix using three VOOHU material numbers: 75Ω, 90Ω, and 120Ω.

The following table only quotes the checkable fields of the VOOHU Chinese and English public page on August 20, 2026. All three models are listed as 2012 sizes, but have different published common-mode impedance, RDC, rated current, and rated voltage. The "Ω typ" in the table are all typical values ​​of common-mode impedance on the page, not USB differential impedance; the webpage does not provide the complete insertion loss curve, S parameters, pin diagram and USB conformance conclusion required for this article.

Can handleWHLC-2012A-750CSet to the A branch with the lower exposed common mode impedance, putWHAC-2012A-900T0Set as the middle branch, putWHLC-2012A-121T1Set to the C branch with the higher exposed common mode impedance. The three boards must share the same PCB, ESD components, connectors, cables, firmware and test conditions, changing only the common-mode inductor or bypass status. If you cannot obtain the impedance and differential curves at the same frequency, you cannot deduce whose USB performance is better based on the three numbers 75, 90, and 120.

5. From schematic to mass production: five steps to close the boundary of signal integrity and EMC

Step One: Freeze profile identity and high-frequency parameter gaps

First freeze the complete material number, specification version, schematic symbols, package, recommended pads and assembly direction. The data list includes at least the common-mode impedance versus frequency curve, differential insertion loss or S-parameters, RDC, rated current/voltage, insulation resistance, operating temperature and welding conditions. Fields that are not available on the web page should be clearly marked to be confirmed by the supplier, and should not be filled in from similar series or other brands.

Step 2: Establish four baselines for bypass, A, B, and C on the same board

Before EMC optimization is performed, first use the bypass board to confirm that the link itself can stably enumerate, transmit, and hot-plug, and then load the three candidates in sequence. Document high-speed eye diagrams or project-approved electrical tests, enumeration times, throughput, error counts, long and short cable lengths, and different host/device combinations.USB-IF USB 2.0 Electrical Conformance Test SpecificationA framework of electrical test criteria that USB 2.0 products should meet is given; internal pre-screening cannot be stated as having obtained USB-IF certification.

Step 3: Measure cable current and radiation under real business conditions

Keep the chassis, cables, port loads, ground planes, and test distances consistent, and compare cable common-mode currents, near-field hot spots, and regulatory scans for bypass and A/B/C candidates. Don’t just pick one frequency point with the greatest improvement, but also observe new peaks, different polarizations, different line lengths, and port idle/continuous transmission status. If the device improves radiation but significantly shrinks the eye diagram, it means that the balance has not been completed, and you need to go back to layout, shielding, reflow or device curves to reselect.

Step 4: Bind ESD test and link status records

Cover power outage, power-on idle, continuous communication and specified load according to applicable product standards, and record contact/air discharge points, polarity, times, levels, reset, disconnection, error count and automatic recovery respectively. When passing ESD, you cannot just look at the appearance of the device, nor can you regard a communication recovery as normal. Connector shielding, ESD grounding, common mode inductor location, and PHY recovery strategies are reviewed as the same system.

Step 5: Cover temperature, cables, hosts and batches before deciding on materials

Before mass production, at least cover the most adverse temperatures and power supplies, multiple hosts and devices, cables of different lengths/structures, multiple device batches and board batches. Compare temperature rise, voltage drop, insertion loss, radiation and functional drift after ESD, and save the original records. Any substitution material changes should be rechecked for complete suffixes, high frequency curves and pad identities; simply "same dimensions, similar impedance numbers" is not enough to inherit the completed verification.

6. Frequently Asked Questions (FAQ)

FAQ: How to choose a USB 2.0 common mode inductor? What should you look for first?

First confirm that the cable common-mode current is indeed the problem and save the signal integrity and EMC baseline of the uninstalled components; then compare the target frequency band impedance, differential S-parameters, symmetry, RDC and packaging. USB 2.0 selection cannot be completed with a single nominal Ω value.

Is the stronger the USB common mode inductance, the better?

no. Higher common-mode impedance may improve certain frequency bands, or it may increase differential losses or parasitics. The goal is EMC improvement and USB electrical margin qualification, rather than pursuing the maximum single point impedance.

What is the USB common mode inductor impedance equal to 90Ω differential impedance?

The two cannot be equated. The common mode impedance describes the common mode path, and the USB channel 90Ω describes the differential transmission line; the nominal 90Ω device does not mean automatic matching, and the curve, S parameters, pad and board-level testing still need to be checked.

Where to place the USB common mode inductor, should the ESD device be in the front or behind?

When two types of devices are really needed, the common USB 2.0 common mode inductor ESD sequence is connector - ESD - common mode inductor - PHY/MCU, with ESD closest to the entrance; in the end, the target PHY, ESD device and grounding information still prevail.

Can two ordinary magnetic beads be used instead of the common mode inductor?

Not to be considered an equivalent substitute. Two independent ferrite beads will directly affect the differential signal of each line, and their impedance matching and parasitic differences may also increase the imbalance. If the project really needs to be compared, the differential and common-mode tests must be redone as separate topologies instead of using the common-mode inductance conclusion.

Can the three VOOHU candidate part numbers be directly used for USB 2.0?

Cannot confirm directly. The public page only proves the candidate identity and the fields in the table; specifications, pins and high-frequency data should be obtained, and the decision should be made after completing USB electrical, EMC and ESD verification on the target PCB.

Conclusion

How to choose a USB 2.0 common mode inductor? The answer is not "find a 90Ω device", but first confirm the common mode noise path, and then put the common mode impedance, differential insertion loss, layout and system testing in the same verification matrix.WHLC-2012A-750C、WHAC-2012A-900T0withWHLC-2012A-121T1A/B/C starting points for 75Ω, 90Ω and 120Ω open fields can be provided; the real final conclusion must still be supported by the current specifications, same-board comparison, USB electrical margin, EMC and ESD results.