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Communication and interconnect · Application solutions

High-Speed Signal Interconnect

LVDS, SerDes and signal conditioning. Part of the "Communication and interconnect" group, which runs from PHYs and switching to industrial buses and pairs each chip with a matching port design.

High-Speed Signal Interconnect solution icon

Typical application circuits

Circuit approaches and matching VOOHU parts, organized by application scenario.

HS-01

LVDS driver and receiver circuit

The LVDS driver and receiver connect over a differential channel, and termination completes the transmission path. Choose the connectors and cables for the link.

  1. Logic signal
  2. LVDS driver and differential channel
  3. LVDS receiver
  • Professional video
  • Industrial control

Core chips (vendor documentation)

Design checklist

  • Do not treat USB, HDMI or CML as LVDS and reuse this circuit for them.
  • Check the transmit and receive levels, termination and supply decoupling.
  • Choose board-to-board cables and connectors by pair impedance.
  • Measure timing and eye diagrams.
HS-02

LVDS filtering and ESD evaluation

Add a common-mode choke and low-capacitance ESD devices between the LVDS transmitter and receiver as needed. Verify the levels and signal loss first.

  1. LVDS transmitter
  2. Optional filter/ESD network
  3. LVDS receiver
  • Professional video
  • Consumer electronics
  • Industrial control

Core chips (vendor documentation)

Matching VOOHU parts

Design checklist

  • Test results decide whether the filter and ESD parts are fitted.
  • Low capacitance does not mean LVDS-compatible. Check it against the channel bandwidth.
  • Check parasitic capacitance, protection clamping and differential-mode insertion loss.
  • Compare eye diagrams and EMC results before and after the parts are fitted.
HS-03

10G SerDes retiming and equalization

The host SerDes signal is conditioned by the CDR and equalization in a 10G retimer. The peripheral parts depend on the channel.

  1. Host SerDes
  2. 10G retimer
  3. High-speed channel/receiver
  • Data communications
  • Professional video

Core chips (vendor documentation)

Design checklist

  • Design LVDS and CML circuits separately.
  • Confirm the link distance and bit error rate by measurement.
  • Check AC coupling and CML common mode for the target protocol and data rate.
  • After configuring the registers, test BER using S-parameters and PRBS.
HS-04

SerDes-to-SFP electrical interface

The host SerDes connects to the SFP module through an electrical channel. The channel budget decides whether a retimer is added. The SFP cage provides only the mechanical fit.

  1. Host SerDes
  2. Channel/optional retimer
  3. SFP module electrical interface
  • Data communications
  • Power grid

Core chips (vendor documentation)

Matching VOOHU parts

Design checklist

  • The electrical design must cover the whole link from the host chip to the SFP module.
  • The SFP cage does not determine 10G channel performance.
  • Check AC coupling, the mating connector, I2C and control pins for the data rate.
  • Check the module power, and run SI and BER tests.

Chip part numbers are taken from the vendors' public documentation and are for selection reference only. Check matching VOOHU parts against your project parameters before use.

Standard reference designs for this solution area are being prepared and will be listed on this page once published. For circuit and part selection support, contact a VOOHU FAE.

Need help selecting parts for your project?

Send the chip model, interface data rate, and power and protection requirements to a VOOHU FAE to check the peripheral parts against a reference design.

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