All four MDI pairs carry bidirectional traffic. The design uses a voltage-mode PHY with on-chip termination, so no additional 49.9Ω termination is added on the data lines, and the PHY-side center taps are not connected to an external bias supply.
Four center taps
CT_A–CT_D each connect to GND through C1–C4 (100nF); place each capacitor close to its LAN transformer pin. The four CTs are not shorted to each other, and no CT is tied directly to ground.
Gigabit LAN transformer and pairs
T1 contains four 1:1 isolation transformers + CMCs, forming a TD structure. A/B/C/D connect in order to RJ45 pins 1/2, 3/6, 4/5 and 7/8; all four are data pairs.
Common-mode termination and shield
The four cable-side CTs each go through R1–R4 (75Ω) to the common BS node, which connects to SHIELD through C5 (1nF / 2kV). The resistors and capacitor are external parts on the board; the RJ45 metal shell connects to the same SHIELD.
Scope
Non-PoE; for architectures with on-chip termination and CTs grounded through capacitors. GND and SHIELD are separate nets; how they relate at the system level is designed separately. Add the PHY's power supply, clock, reset and MAC interface according to the specific part selected.
How to read the Gigabit Ethernet port schematic
Applies to: voltage-mode architectures with on-chip termination and CTs grounded through capacitors.
CT_A–CT_D each connect to GND through C1–C4 and are not shorted to each other.
All four pairs are data pairs; RJ45 pins 4/5 and 7/8 are not shorted.
R1–R4 and C5 are external Bob Smith parts on the board.
GND and SHIELD are separate nets; function names do not represent package pin numbers.
The part numbers above are the VOOHU parts listed under "Product illustrations" in this reference design PDF, for selection reference. Verify the final part numbers item by item against the PHY vendor documentation and the circuit parameters.
Need a quote or samples for these parts? Send your quantity and PHY model to a VOOHU FAE, who will check the part selection against this reference design.
Limited to Gigabit PHYs with on-chip MDI termination whose PHY-side CTs are grounded through capacitors. Therefore no additional 49.9Ω is added on the data lines, and no external supply is applied to the CTs. This is not a connection that applies unconditionally to every voltage-mode PHY.
E1 pp. 114–115; E2 pp. 3–4; E4 p3
C1–C4 / 100nF
4, outside T1
Connect CT_A/CT_B/CT_C/CT_D to GND respectively, giving each pair's common-mode signal an AC return path and blocking DC in that branch. The four CTs are independent of each other; each capacitor sits right next to its own pin, and they are not merged into one.
E1 p115 Figure 9-2; E2 p4 §4.2
T1A–T1D / 1:1
4 channels, inside T1
The four isolation transformers carry the A/B/C/D differential signals respectively. Each PHY-side CT goes to ground only through its own capacitor; each cable-side CT is brought out to its own 75Ω. Confirm inductance, insertion loss, return loss, crosstalk and insulation ratings for the selected PHY.
E1 pp. 115–116; E3 p5 Figure 3
CMC_A–CMC_D
4 channels, inside T1
In each channel, a two-winding common-mode choke sits in series on the two cable-side data lines to suppress common-mode noise. Together with the isolation transformer it forms the TD structure, with no autotransformer winding; Bob Smith termination is taken from the transformer's cable-side CT.
E3 pp. 4–5, Figure 3
R1–R4 / 75Ω
4, outside T1
Connect each of the four cable-side CTs to the common BS node. Each CT passes through its own 75Ω before they join, forming the common-mode termination; the four CTs are not tied together directly. The 75Ω resistors serve common-mode termination and are not placed in series in the differential data path.
E1 p115 Figure 9-2; E2 p4 §4.2
C5 / 1nF, 2kV
1, outside T1
BS is AC-coupled to SHIELD through C5, which also blocks DC. The values come from the vendor's example. The 2kV marking must be turned into a specific part rating and checked against the system-level insulation test; it cannot be taken as equivalent to 2kVac or a surge rating.
E1 p115 Figure 9-2; E2 p4 §4.2
J1 / discrete RJ45
1, no magnetics
A→1/2, B→3/6, C→4/5, D→7/8, with the same P/N polarity on every pair. 1000BASE-T carries data on all four pairs, so neither 4/5 nor 7/8 is shorted; the metal shield shell connects directly to SHIELD.
E1 p115 Figure 9-2; E2 p4 Figure 4-1
GND / SHIELD
Two nets
C1–C4 connect to GND, the PHY circuit ground; the other end of C5 and the RJ45 shell connect to SHIELD. Whether the system uses coupling parts, and how it connects to the chassis or PE, must be decided based on the product's mechanical design, EMC and insulation requirements.
E1 p115 Note D; E2 p4, §8.2
Vendor documentation and scope of use
E1 · Texas Instruments DP83867IR/CR, SNLS484J, revised 2026-06. pp. 114–116, Figure 9-2: on-chip termination, four independent 0.1µF capacitors, pair mapping, and 75Ω + 1nF/2kV.
E2 · Microchip KSZ9131MNX Hardware Design Checklist, DS00003371A, 2020. pp. 3–4, §4.1/4.2, Figure 4-1: no external termination/bias, independent CT capacitors and a common Bob Smith capacitor.
E3 · Microchip / Microsemi ENT-AN0098 / VPPD-01740, Rev.2.2, 2018-06. Body text pp. 4–5, Figure 3 (PDF pp. 6–7): isolation transformer + cable-side two-winding CMC, and where the cable-side CT termination connects.
E4 · Motorcomm "YT8511 Application Note" V1.2, p3 "MDI interface". A public repost of a document attributed to the vendor: used to cross-check voltage-mode output, on-chip termination and 100nF to ground. Check the current version with the vendor when selecting parts.
Limits of use
This design is a non-PoE MDI interface reference. Once the specific PHY, LAN transformer and port protection are selected, re-check the values, package pin numbers and system grounding, and complete link, MDI, EMC and insulation testing. Document and schematic review is not a substitute for hardware validation. Layout requirements: route the four MDI pairs at 100Ω differential impedance and control intra-pair skew and stub length; connect the CT capacitors to GND as close as possible. Keep the magnetics isolation zone, and handle power/ground copper according to the PHY and LAN transformer vendors' layout rules. Bob Smith is only a common-mode termination; it does not provide ESD or surge clamping.
Gigabit Ethernet port circuit FAQ
How do the RJ45 pins map on a Gigabit Ethernet port? Can 4/5 and 7/8 be shorted as in 10/100 Mbps designs?
No. 1000BASE-T carries data on all four pairs: A→1/2, B→3/6, C→4/5, D→7/8, with the same P/N polarity on every pair, and neither 4/5 nor 7/8 is shorted. Instead, the Bob Smith common-mode termination is taken from each of T1's four cable-side CTs through its own 75Ω resistor and joined at the common BS node.
Can the four center taps be tied together to share one capacitor?
No. CT_A–CT_D each connect to GND through C1–C4 (100nF). The four CTs are not shorted to each other, and no CT is tied directly to ground; each capacitor sits right next to its LAN transformer pin, and they are not merged into one. The same applies on the cable side: each of the four CTs first passes through its own 75Ω before they join, and they are not tied together directly.
Does a voltage-mode Gigabit PHY still need 49.9Ω termination or a supply on the center taps?
Not in this design. The precondition is a Gigabit PHY with on-chip MDI termination whose PHY-side CTs are grounded through capacitors, so no additional 49.9Ω is added on the data lines and no external supply is applied to the CTs. This is not a connection that applies unconditionally to every voltage-mode PHY; verify it against the selected PHY's documentation.
The Bob Smith capacitor is marked 1nF/2kV. How should the 2kV be read when choosing the part?
1nF/2kV comes from the vendor's example; C5 AC-couples BS to SHIELD and blocks DC. The 2kV must be turned into a specific part rating and checked against the system-level insulation test; it cannot be taken as equivalent to 2kVac or a surge rating. Bob Smith is only a common-mode termination; it does not provide ESD or surge clamping.
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