10/100BASE-TX RJ45 with Integrated Magnetics Schematic (Current-Mode PHY) · Standard reference design schematic (D2.6)
Key points: connecting an RJ45 with integrated magnetics
Scope
For non-PoE 10BASE-T/100BASE-TX interfaces. The PHY must use external termination, and both PHY-side center taps must be allowed to connect to the bias supply. VBIAS is typically 3.3V; set the actual value per the PHY specification.
PHY-side termination and bypassing
TD± and RD± connect to TX± and RX± of J1, respectively. R1–R4 are 49.9Ω±1% each; each signal line is pulled up to VBIAS through one resistor, which provides termination and bias. C1/C2 (100nF each) are placed close by and bypass to GND. CT_TX and CT_RX connect to VBIAS; C3/C4 (100nF each) connect to GND, each placed close to its CT.
Isolation and cable-side connection
J1 contains two 1:1 isolation transformers and common-mode chokes (CMCs). In standard MDI, TX± connects to RJ45 cable contacts 1/2 and RX± to 3/6. Automatic swapping of the transmit and receive pairs requires a PHY that supports Auto-MDIX; polarity within each pair must still match.
Bob Smith termination and shielding
The TX and RX cable-side CTs and the unused pairs 4/5 and 7/8 connect to BS through Ra, Rb, Rc and Rd respectively (75Ω each). BS connects to SHIELD through the internal Cb (1nF) and BS_RET; do not add these again externally. SHELL connects directly to the same SHIELD. How GND, SHIELD and protective earth (PE) are connected is determined by the system design.
Insulation and implementation requirements
HV*: The TI guide recommends that Cb be rated for at least 2kV; verify the voltage rating type and test conditions against the part specification. Bob Smith termination provides common-mode termination and does not replace surge protection. Place R1–R4 and C1/C2 close to the PHY, and route the MDI traces for 100Ω differential impedance. Design the PHY power, clock, reset and configuration separately. The product images show appearance only; when selecting parts, check the internal circuit and the actual solder pins.
How to read the schematic: RJ45 with integrated magnetics
Applies to: current-mode architectures with external 49.9Ω termination, where both PHY-side CTs are allowed to connect to VBIAS.
C1–C4 are all bypass capacitors. C1/C2 sit close to the termination; C3/C4 sit close to their respective CTs.
Components inside the dashed box are internal to J1; do not add another Bob Smith network externally.
All VBIAS labels are the same net; all GND labels are the same net; GND and SHIELD are separate.
A solid dot on a wire indicates a connection; a crossover arc indicates no connection; a dot next to a winding marks its polarity (dot convention).
HV*: TI recommends a Cb voltage rating of at least 2kV; verify the actual voltage type, test conditions and module insulation specifications. Map the functional pin names to the actual solder pins of the selected part.
The part numbers above are the VOOHU parts listed under "Product images" in this reference design PDF, for selection reference. Check the final part numbers item by item against the PHY vendor documentation and the circuit parameters.
Need a quote or samples for these parts? Send your quantity and PHY model to a VOOHU FAE, who will check the part selection against this reference design.
Limited to 10/100 Mbps architectures with external termination and both PHY-side CTs connected to the bias supply. Verify the VBIAS value and the complete power, clock, reset and configuration against the selected PHY.
E3 pp. 68–69; E2 p4
R1–R4 / 49.9Ω±1%
4, outside J1
Each TD± and RD± line connects to VBIAS through one resistor, forming termination and bias. The termination common node does not connect directly to GND. Place R1–R4 close to the PHY.
E3 p69 Figure 7-2; E2 p4 Figure 3-4
C1, C2 / 100nF
2, outside J1
Each connects between the VBIAS node of one termination pair and GND, providing local bypassing for high-frequency current. Place each close to its termination resistors.
E3 p69 Figure 7-2; E2 p4 §3.2
C3, C4 / 100nF
2, outside J1
CT_TX and CT_RX connect directly to VBIAS, and each is bypassed to GND by its own nearby 100nF capacitor. Keep one per channel as in the vendor configuration; do not omit local bypassing just because the CTs share a net.
E3 p69 Figure 7-2; E2 p4 §3.2
TX/RX transformers / 1:1
2, inside J1
Pass the differential signal and isolate the PHY from the cable. The PHY-side CTs connect to VBIAS; each cable-side CT connects to BS through 75Ω. Match the turns ratio, polarity (dot) terminals and magnetic parameters to the selected PHY and module.
E3 p69 Figure 7-2; E4 p5
CMC / common-mode choke
2, inside J1
On the cable side of the transformers, one in series with each of the two data pairs, suppressing common-mode noise with common-mode impedance. The module's insertion loss, return loss, balance and common-mode characteristics must still meet the interface requirements.
E1 p7 §2.4; E4 p5
Ra–Rd / 75Ω
4, inside J1
Ra and Rb connect the TX and RX cable-side CTs to BS, respectively. Contacts 4/5 are shorted together and then connect to BS through Rc; contacts 7/8 are shorted together and then connect to BS through Rd. Each of the four branches reaches the common node through its own 75Ω. This applies only within the 10/100 Mbps, non-PoE scope of this design.
E1 p6 §2.3; E4 p5
Cb / 1nF, HV*
1, inside J1
BS connects to SHIELD through Cb and BS_RET, forming a high-frequency common-mode return path while blocking DC. TI recommends a voltage rating of at least 2kV; verify the voltage type, test conditions and internal capacitor specifications separately. This rating is not a surge rating.
Capacitance / internal: E4 p5; Voltage recommendation: E1 p6
J1 / RJ45 and shield terminal
1 integrated module
Standard MDI: TX+/- map to contacts 1/2 and RX+/- to 3/6; Auto-MDIX requires PHY support. SHELL and BS_RET connect to the same SHIELD outside the module. Contact numbers are not PCB solder pin numbers.
E3 p69 Figure 7-2; E4 p5; E1 p7
GND / SHIELD
Two reference nets
C1–C4 connect to circuit GND; the shield side of Cb and the metal shell connect to SHIELD. This schematic has no GND-SHIELD coupling network; how the chassis connects to PE is determined by the system design.
E1 pp. 6–7; E4 p5 (structure)
Vendor documentation and scope of use
E1 · Texas Instruments AN-1469 / SNLA079D, Rev. D, 2013-04, pp. 4–7, p13: termination layout, 100Ω differential routing, 75Ω + 1000pF common-mode termination, and the recommendation that the capacitor be rated for at least 2kV.
E2 · Texas Instruments DP83848 to DP83826A Hardware Rollover Document, SDAA089, 2025-09, p4 §3.2 / Figure 3-4: current-mode external termination, CTs connected to the bias supply, and 100nF per channel.
E3 · Texas Instruments DP83848C/I/VYB/YB, SNLS266E, 2015-03, pp. 68–69, Figure 7-2: 49.9Ω, four 0.1µF capacitors and the 1:1 magnetics connection for the 10/100Mb/s interface. The conditions of use must match the selected PHY.
E4 · Pulse Electronics J403.K, 2012-08, p5, internal diagrams of the J0011 and other series: cable-side CMC, 4×75Ω and internal 0.001µF. The public copy of the vendor document used supports this structure. That page does not give the Cb voltage rating, and it does not prove that the parts shown here are a match.
Limits of use
This is a reference design for a non-PoE, specific current-mode MDI architecture. After the actual PHY and RJ45 with integrated magnetics are selected, you still need to check ratings, solder pins and system grounding, and complete link, EMC, insulation and other validation. A document and schematic review does not replace prototype testing.
FAQ: RJ45 with integrated magnetics
With a current-mode PHY, do the LAN transformer center taps connect to 3.3V?
Connect them to the bias supply. In this design, CT_TX and CT_RX both connect to VBIAS. VBIAS is typically 3.3V; set the actual value per the PHY specification. Each CT also needs its own 100nF capacitor (C3, C4), placed close to that CT and bypassing to GND. This assumes the PHY uses external termination and both PHY-side CTs are allowed to connect to the bias supply.
How do I connect the 49.9Ω termination resistors? Can the common node go directly to ground?
Not directly to GND. Each TD± and RD± line is pulled up to VBIAS through its own 49.9Ω±1% resistor, which provides termination and bias. The VBIAS node of each termination pair is then bypassed to GND by a nearby 100nF capacitor (C1, C2). Place R1–R4 and C1/C2 close to the PHY, and route the MDI traces for 100Ω differential impedance.
CT_TX and CT_RX connect to the same VBIAS. Can I drop one of C3 and C4?
Not recommended. Following the vendor's per-channel configuration, this design keeps both C3 and C4 at 100nF each, each placed close to its CT and bypassing to GND. Do not omit local bypassing just because the two CTs share a net. All four capacitors, C1–C4, are bypass capacitors: C1/C2 for the termination nodes and C3/C4 for the center taps.
With an RJ45 with integrated magnetics, do I still need to add a 75Ω and 1nF Bob Smith network on the board?
No, do not add it again. J1 contains four 75Ω resistors, Ra–Rd, and Cb (1nF). The TX and RX cable-side CTs and the unused pairs 4/5 and 7/8 connect to BS through 75Ω, and BS is brought out through Cb and BS_RET. Externally, you only need to connect BS_RET and SHELL to the same SHIELD. Verify the Cb voltage rating against the module specification.
If the transmit and receive pairs are swapped, can the port adapt automatically?
It depends on the PHY. In standard MDI, TX± connects to RJ45 cable contacts 1/2 and RX± to 3/6. Automatic swapping of the transmit and receive pairs requires a PHY that supports Auto-MDIX, and polarity within each pair must still match. Also note that contact numbers are not PCB solder pin numbers; after selecting the part, map them to its actual solder pins.
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